Digital Lab Projects Design

The number of unknowns that came with this project made it challenging to develop a detailed plan of action, even after establishing an area to focus on. As such, the team decided to establish broad goals so as to remain flexible to any changes or setbacks. This was achieved while minimizing the likelihood of falling significantly behind schedule through the implementation of some of the Agile/Scrum development framework principles which focus more on maximizing team productivity on a weekly basis over strictly adhering to a set project schedule.

The established plan was as follows:


 * Research hardware, software, and other tools as necessary


 * Run a simple project, supplied by Dr. Frenzel’s course, on Amazon FreeRTOS


 * Investigate FreeRTOS+TCP/IP stack


 * Implement UDP and document


 * Implement TCP and document


 * Implement HTTP Server and document

=Problem Definition=

Background
The Distributed Processing and Control Networks course offered by the University of Idaho uses a real-time operating system called the FreeRTOS kernel for project-based learning. When originally incorporated into the course, this software was maintained by its developers at Real Time Engineers but has since been acquired by Amazon Web Services (AWS), and has undergone some notable expansions. These changes include the inclusion of the FreeRTOS+TCP library into the main FreeRTOS repository. Upgrading to the newest iteration of the software is desirable to ensure that current concepts and technologies are being taught.

Hardware
=Design Considerations=

Public Health, Safety, and Welfare

Currently the project would be unsafe for any use outside of an educational setting. With further development however, and extensive testing the project could perhaps be pushed in the direction of medical applications that rely on networking.

Global Factors

The project pulls from a variety of resources available online and is web accessible suggesting a possible global impact. Many systems rely on network communications mechanisms as well, so in theory this project could be pushed in that direction.

 Cultural Factors 

The project is currently written in English, offering limited opportunity for cultural impact.

 Social Factors 

The project intends to positively impact public education

 Environmental Factors

The project avoids waste by reusing available hardware.

 Economic Factors 

The project reduces development costs by providing a stepping stone for further research.

=Project Learning= In order to achieve the desired goals a lot of time was spent becoming familiar with the different parts that made up the project. This entailed developing a sufficient understanding of both the Cerebot MX7cK development board and Amazon FreeRTOS architectures.

Cerebot MX7cK
The Cerebot MX7cK development board is based on the Microchip PIC32MX795F512L microcontroller and is designed to be accessible to anyone interested in embedded control and network communications applications. It provides 52 I/O pins which support peripheral functions such as the UART, SPI, and I2C ports along with five pulse width modulated outputs and five external interrupt inputs. The board provides a standard 10/100 Ethernet interface composed of a 10/100 Ethernet Medium Access Controller (MAC), internal to the board’s microcontroller, and an SMSC LAN8720 Ethernet Physical Layer Transceiver (PHY), external to the board’s microcontroller. This allows for the ability to establish a connection between 10Mbps or 100Mbps Ethernet networks (see Fig 2 for visual reference).

Ethernet Controller
In order to successfully implement the FreeRTOS+TCP stack a network interface port layer was needed for the Cerebot MX7cK development board. This involved generating code to initialize the Ethernet Controller.

LAN8720 Physical Layer Transceiver
The LAN8720 PHY chip is a hardware component that transmits and receives on Ethernet cables and telephone wires. It interfaces to the MAC layer via the Reduced Media Independent Interface (RMII), a standard interconnection between the MAC and the PHY for communicating data. Because the PHY is external to the microcontroller it must be accessed through a special set of registers called Media Independent Interface Management (MIIM) registers. These registers allow users to configure, control, and collect status information on the module’s operations.

FreeRTOS Kernel
FreeRTOS is a popular real-time operating system kernel distributed under the MIT open source license. It is intended for embedded applications, allowing users to break code into sets of independent tasks and ensuring timely and deterministic responses to events while requiring minimal ROM, RAM, and processing overhead. It comes with an extensive set of libraries that afford users with a wide variety of built-in support for developing their applications.

=Project Design=

FreeRTOSv.8.2.2 Reference Design Project
As it stands, the Distributed Processing and Control Networks course already offers a reference design projects using functionality from FreeRTOSv.8.2.2 on its website as a platform for students to base their projects off of. This reference design project was used as a base for developing the updated reference projects so as to maintain as much of the previous file structure and project settings used in the existing template as possible. This was done with the hope that it would minimize the amount of time Dr. Frenzel would need to familiarize himself with these new projects once they were delivered. It also provided a basic main function and supporting board initialization functionality which saved the time it would require to develop these from scratch.

The FreeRTOS Website
The FreeRTOS website offers a FreeRTOS+TCP Tutorial which proved instrumental in the process of integrating the FreeRTOS+TCP library into the base FreeRTOS Reference Design Project and the subsequent development of the new reference design projects which utilized it.

Public GitHub Repositories
The GitHub project "FreeRTOS-TCP-for-PIC32" from user jjr-simiatec as well as the GitHub project "storage" from user rjvo were used as sources of code for our new projects. The "FreeRTOS-TCP-for-PIC32" project offered a network driver as well as templates for a required PHY driver which were used for both the TCP echo server as well as the UDP packet spitter projects for controlling the Cerebot’s network communication hardware. The "storage" project had a task that was used for receiving and echoing TCP packets from an established TCP socket.

Vending Machine Code
The Vending Machine project currently offered on the Distributed Processing and Control Networks course website was heavily drawn upon in order to create the HTTP server demo. The functionality of this project essentially stayed the same but was rearranged to execute within FreeRTOS tasks.

=Project Testing=

MPLAB Debugger
As a microchip board, the Cerebot was programmed using the MPLAB X IDE which includes built-in debugging functionality. This was used to validate code functionality and discover bugs in system execution.

Wireshark
Wireshark is widely-used multi-platform network protocol analyzer, allowing users to closely monitor and analyze network traffic(?) and behavior. This tool can read off live data from Ethernet, making it very useful for verifying the performance of the projects that were built. It can also track data from Bluetooth, USB, and others, which would be useful to have in the future should the project be expanded upon.

Putty
Open-source terminal emulator used to establish a TCP socket connection with the Cerebot.

=Deliverables=
 * The team successfully determined the hardware and software components most applicable to the needs and scopes of the project.


 * Provided code samples utilizing the FreeRTOS+UDP and FreeRTOS+TCP stacks, as well as an HTTP server example, giving a platform from which projects for the Distributed Processing and Control Networks course can be developed in the future.



=Team Information=

=Additional Documentation= Team Contract

Team Contract

Meeting Minutes

Meeting Minutes Folder

Design Review

Design Review

Final Report