FPGA Data Acquisition

=Problem Definition= Our main objective is to create a cheap, modular FPGA data acquisition and control system using commercial, off-the-shelf parts. Our design uses a Red Pitaya FPGA in order to take in two analog inputs. Once we have these, our web application allows users to control the output signal through a PID loop. This output is then downloaded as a CSV file onto the connected computer. Our design has a wide variety of lab applications and can be useful for anything from laser modulation to circuit analysis. Traditional data acquisition systems are very expensive due to their degree of specialization. An affordable and flexible solution would be desirable for many companies looking to process multi-phase inputs.

=Background= Our project is sponsored by Thorlabs, which is historically an optomechanics company, that is pushing to provide better electronics for instruments and instrument systems. This typically involves the handling of analog control signals that interact with some digital controller. The goal of our project is to expand Thorlabs portfolio by creating an FPGA-based Data Acquisition/Controller device.

A similar Capstone project was sponsored by Thorlabs last year, and this project will seek to expand upon their work, which was done with an FPGA development board made by Red Pitaya. The previous team was able to create some custom hardware for the purposes of Thorlabs, however, they encountered difficulty when attempting to load this hardware onto the FPGA. This served as the entry point for our team, whose first major decision involved whether to use our budget to purchase new FPGAs or to attempt to resolve the issues with the Red Pitaya.

FPGA
A field-programmable gate array (FPGA) is a type of re-configurable integrated circuit. This allows users to program the FPGA and create new circuits in physical hardware, making them more adaptable than a chip with only programmable software. This adaptability often can allow for faster computations done at the hardware layer, rather than in software, and make the FPGA a good fit for flexible data acquisition systems like the one being designed in this project.

STEMLab 125-14 Red Pitaya
The Red Pitaya is an FPGA with built-in ADC, and DAC converters, each operating at 125 MSPS with 12-bits of resolution. This makes it a good fit for our project because it doesn't require peripheral hardware to capture or produce signals.

The Red Pitaya utilizes a Zynq 7000 SoC which is composed of an FPGA and ARM-based processor which run together. The FPGA is programmed using a bitstream, and will typically be programmed with a .bit file provided by Red Pitaya which gives us access to many useful hardware modules. The processor runs a version of Ubuntu Linux and has access to FPGA through memory-mapped registers.



=Specifications= In the world of microcontrollers, the cost of data acquisition systems represents a major hurdle for many companies. Acquiring the hardware and software combination in order to process multi-phase inputs can put a big dent in a project’s budget. Furthermore, many data acquisition and control systems that are available are highly specialized which prevents use across different platforms. Our goal is to create a cheap, modular FPGA data acquisition and control system using easily available off the shelf hardware. This solution will be affordable and portable, which allows use across many different system types and a multitude of applications.

Thorlabs will provide a testing setup, which uses our controller as a component in a Pound Drever Hall loop.

To make a clearer path for our project, the requirements of our project were split into 3 tiers.

Tier 1
Tier 1 represents our primary objective of creating a dual channel data	acquisition device. In this case, dual channel data acquisition must include support not only logging, but also filtering, and decimation up to 16 bits of resolution. These features should also ideally be implemented through hardware in the FPGA to fully utilize our board.

Tier 2
Tier 2 represents our projects secondary objective of implementing a controller which acts alongside the logger. This controller should start as a simple proportional controller and be scaled to PID control if proportional control proves insufficient for laser control.

Tier 3
Tier 3 represents system modularity, which would allow a dual channel control system to expand to quad channel by running another controller alongside it in parallel. This tier is considered our project’s stretch objective because of our limited time.

=Design= The design of our system will be based on open-source web-server applications provided by Red Pitaya which implement tools like an oscilloscope. These web applications are built using a frontend and backend which communicate using the JSON data format.

FrontEnd
The front end is implemented using HTML, CSS, and Javascript. The HTML and CSS provide a graphical user interface for our application, while Javascript is used to implement the logic that corresponds to a backend C++ controller.

BackEnd
The C++ controller and FPGA make up the backend of the system. The C++ controller is used to interact with the FPGA through memory-mapped registers. Many Red Pitaya applications, including ours, also use a standard .bit file to program the FPGA. This removes our need to create custom hardware in order to access features like analog signal processing, decimation, and PID control.



=Validation=

=Team Members= Jacob Jackson Major: Computer Engineering Email: jack0501@vandals.uidaho.edu

Taylor Stewart Major: Computer Engineering Email: stew5398@vandals.uidaho.edu

Cameron Williams Major: Computer Engineering Email: will6599@vandals.uidaho.edu

=Additional Documentation= Project Schedule Meeting Minutes Client Interview