FPGA Data Acquisition

=Problem Definition= In the world of microcontrollers, the cost of data acquisition systems represents a major hurdle for many companies. Acquiring the hardware and software combination in order to process multi-phase inputs can put a big dent in a project’s budget. Furthermore, many data acquisition and control systems that are available are highly specialized which prevents use across different platforms. Our goal is to create a cheap, modular FPGA data acquisition and control system using easily available off the shelf hardware. This solution will be affordable and portable, which allows use across many different system types and a multitude of applications.

=Background= This project builds off of a previous team's work with Thorlabs found here. For this reason, we will continue to use the two STEMLab 125-14 Red Pitaya FPGA boards purchased by the last team. In addition, we also invested in a third Red Pitaya board to allow for all three students to work on the project in parallel.

FPGA
A field-programmable gate array (FPGA) is a type of re-configurable integrated circuit. This allows users to program the FPGA and create new circuits in physical hardware, making them more adaptable than a chip with only programmable software. This adaptability often can allow for faster computations done at the hardware layer, rather than in software, and make the FPGA a good fit for flexible data acquisition systems like the one being designed in this project.

STEMLab 125-14 Red Pitaya
The Red Pitaya is an FPGA with built-in ADC, and DAC converters, each operating at 125 MSPS with 12-bits of resolution. This makes it a good fit for our project because it doesn't require peripheral hardware to capture or produce signals.

The Red Pitaya utilizes a Zynq 7000 SoC which is composed of an FPGA and ARM-based processor which run together. The FPGA is programmed using a bitstream, and will typically be programmed with a .bit file provided by Red Pitaya which gives us access to many useful hardware modules. The processor runs a version of Ubuntu Linux and has access to FPGA through memory-mapped registers.

=Specifications= The functionality of the system can be broken into tiers, which correspond to their priority.

Tier 1 – Dual channel data acquisition with support for decimation and filtering. Graphical User Interface implemented through the Red Pitaya web server.

Tier 2 - Dual PID control using each of the DACs.

Tier 3 - Quad-channel data acquisition.

Writing data to disk is a fundamental aspect of the project; The sponsor is open-minded about the data volume, but making it seamless is important (1 Megasample/second is a good start, but more or less is acceptable)

The client made no UI requirements, though the software accompanying the product should make the process of extracting the data from the acquisition system for analysis as simple as possible.

=Design= The design of our system will be based on open-source web-server applications provided by Red Pitaya which implement tools like an oscilloscope. These web applications are built using an HTML & CSS front-end which interacts with a C++ controller on the Red pitaya using Java Script. Each of these applications also uses a standard .bit file to program the FPGA, removing our need to create custom hardware in order to access features like analog signal processing and PID control.

=Validation=

=Team Members= Jacob Jackson Major: Computer Engineering Email: jack0501@vandals.uidaho.edu

Taylor Stewart Major: Computer Engineering Email: stew5398@vandals.uidaho.edu

Cameron Williams Major: Computer Engineering Email: will6599@vandals.uidaho.edu

=Additional Documentation= Project Schedule Meeting Minutes Client Interview