Campus Facilities Load Shedding Design

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The project aims to design a microgrid load shed algorithm to balance power on the University of Idaho island when Avista undergoes a blackout event. We will determine which campus buildings get power and the priority of the buildings. The loads will be grouped in a logical way to effectively reduce overloading on University of Idaho microgrid generation.

Team Members
Team Name Take a Load Off
Duration Spring 2019 - Fall 2019
UI Facilities
  • Fred Pollard
  • Gene Gussenhoven
  • Marc Compton
  • Scott Smith
Mentors
  • Dr. Herbert L. Hess
  • Dr. Joseph Law
Team Members
  • Kenny Sheffler
  • Lingchao Sun
  • Mohammed Subahe
  • Simeon Drapeau

Introduction[edit]

Background[edit]

The overall UI microgrid scope includes the entire campus, with a total of 143 buildings, excluding Northern farms. Currently, 12% of the campus load is expected to be provided by the new Steam Plant turbines, of which 3% must provide electricity for the Steam Plant.The turbines are expected to be placed in service by Fall 2020. The remaining 9% of annual power production has been allocated for our load shed product. Our project scope includes designing the load shed algorithm for the following campus buildings: McClure, CNR, GJL, BEL. The current microgrid generation considered for this project includes the steam turbines in the Steam Plant and solar panels to be placed on the roof of IRIC. We will aim to design a module load shed scheme that can be scaled when more generation sources are determined for the UI microgrid.

Problem Definition[edit]

1.The UI does not have a systematic control system to control microgrid loads.

2. A load shed algorithm is required to efficiently regulate microgrid power.

Project Goals[edit]

1. Load shed algorithm to allocate the Steam Plant and IRIC power generation efficiently and safely

 a. Load prioritization for McClure, CNR, BEL, and GJL 
One-line












 b. Easily modifiable load-shed algorithm
 c. Determination of switchgear required to implement the system
 d. Load shed system to be modularized to allow for microgrid expansion

2. System testing and verification with Real Time Digital Power System Simulator (RTDS) and SEL equipment

Microgrid Simulation Design[edit]

Specifications[edit]

Our goal is to utilize SEL equipment to implement an efficient system to allocate power from the UI Steam Plant to local campus buildings during Avista blackouts. SEL equipment has functions such as automatic bus synchronism, trip/close commands to remote enabled breakers and so on.

Equipment Description
SEL 751A.png
The SEL-751A’s will be used to replicate the tie relays to the Avista grid and the building relays. They will be used in Dr. Brian Johnson’s lab to test the system designed by our team.
SEL-3530.jpg
The SEL-3554 Real-Time Automation Controller (RTAC) will provide complete and flexible system control for this project.
RTDS-Simulator.jpg
A Real Time Digital Power System Simulator (RTDS) can simulate many different fields, especially for equipment close-loop testing, such as protection relays and different control systems. The RTDS which is located in Dr. Johnson’s lab will be used to simulate the UI micro grid.
Amplifier LVC 5050.png
LVC 5050: The dual channel power supply amplifier has been built for the high power systems. It can deliver op to 2500 W for 2-ohm loads and 5000 W for 4-ohm loads.
Amplifier LV 3622.png
LV 3622: A single channel linear amplifier, specifically designed to drive high impedance loads at high voltage levels.

System Overview[edit]

Campus Microgrid One-Line

This figure illustrates the microgrid one-line for the University of Idaho. The generation in this microgrid includes the Steam Plant turbines and IRIC solar. The loads include many buildings that will not be included in the load-shed scheme as well as the four priority buildings. The last two relays in this system will include two tie relays on either side of the microgrid. These tie relays will be responsible for islanding the system as well as returning to the utility.

Alternatives[edit]

Alternative1

This figure showcases the system we plan on testing using a Real Time Digital Power System Simulator (RTDS) in Dr. Johnson’s lab. We plan to use nine SEL-751 relays and an SEL Real Time Automation Controller (RTAC). The relays included will be the two tie relays, two relays on the microgrid generation, four priority buildings, and one non-priority building. The building priority number is listed after the name.

Alternative2

Our test design consisted of nine SEL-751 relays and one SEL-RTAC. Due to the fact that we donated six SEL-751A relays, we reduced the original design of nine relays to six. The other alternative is to remove the IRIC, GJL, and non-priority buildings so that we can still illustrate load- shedding while maintaining the realistic fact that the microgrid will have two utility ties. The downfall of this alternative is we lose a priority building. In this way, we can show the process of island, load reduction, power balance and grid reconnection.

Alternative3

The last alternative is to remove the Avista eastern tie, IRIC, and non-priority buildings so that we can keep the four priority buildings including McClure, CNR, GJL, BEL, according to the requirements of the facilities. The remaining two relays are then assigned to the Steam Plant and Avista western tie. This design setup was selected because facilities wanted to see load shedding with four buildings. Future teams may choose to add the eastern tie to the design set up. As a note, we simulated one non-priority building internally in RTDS so we did not need a physical relay.

Hardware in the Loop Design[edit]

Hardware in the Loop Design

This figure shows the hardware in the loop design. We use a RTDS to test our load shedding algorithm, because the RTDS equipment can provide real time analog voltages and currents to SEL-751A relays. The HMI runtime model can also work with RTDS in real time. The amplifier consists of six voltage amplifiers and six current amplifiers. After amplification, low-level voltage and current can be converted into high-level voltage and current and finally delivered to the relay.

Communications[edit]

Load-Shedding Algorithm

The 6 SEL relays in this network represent one western tie relay, one relay on the Steam Plant, four relays on the load shed buildings. These smart devices must communicate to the RTAC in order for power to be balanced and for the system to respond to utility events appropriately. We decided to use IEC 61850 GOOSE and MMS communication network to pass information to/from the RTAC and relays.

RTAC Algorithm[edit]

Load-Shedding RTAC Algorithm

This figure shows the inputs and outputs from the RTAC. Ideally, this controller would be centrally located at the Steam Plant. The controller is to take information from the relays on the system and issue the appropriate commands to operate the microgrid system. The utility ties will communicate their breaker status to the RTAC as well as the power flow into the system. The Steam Plant relays will communicate the power generation (real and reactive) as well as the frequency.The last relay type included in our network is the non-priority building relays. These relays will send power consumption (real and reactive) and receive open/close commands from the RTAC. This load and relay was simulated in RTDS and will not send or receive signals from the RTAC.

RTAC Initial Islanding Algorithm

Our RTAC algorithm begins with islanding. The UI system will island when the voltage drops for a set amount of time on the Avista bus. This logic will be implemented by using the 27 element (undervoltage) in the west tie. When this element is asserted, it is sent to the RTAC so it can implement the appropriate decisions to balance the island. This logic is represented the first box in the figure. The controller will receive power from the Steam Plant and tie relays, and will use this information to calculate how much power will need to be shed when the tie breaker is opened. Once this event occurs, the calculated load shed required will be used to trip campus buildings based on priority.

RTAC Power Balance Algorithm

Once the microgrid is in island mode, the power must be constantly balanced within the system. Our team is using two schemes to balance power. The first is contingency load shedding. A contingent load shed scheme compares the power generation to the power consumption and adds or removes load based on this comparison when the contingent event occurs. The second scheme is frequency/voltage-based load shedding. The frequency of the steam turbines and the voltage of the island bus will be monitored in the microgrid system. If either the frequency or voltage begins to drop, load will be shed to restore the power balance.

Return to Utility Logic

The last action the RTAC must implement is returning the microgrid system to the Avista grid. The tie relays would ideally implement most of this logic. However, the SEL-751A relays used in the test setup do not have a synchronism check element. Therefore, the synchronism check will be implemented in the RTAC. This figure shows when the voltage returns to the Avista bus for a certain amount of time, the RTAC begins a synchronism check. This synchronism check verifies the voltage, frequency, and phase on the Avista bus and the UI microgrid match. Once the sync check is satisfied, the UI microgrid is connected back to the grid. The RTAC then closes all of the UI microgrid campus buildings back into the grid.

Microgrid Simulation Testing[edit]

RTDS Draft[edit]

RTDS Draft

The RTDS Equipment in Dr. Brian Johnson’s lab was utilized to test the load shedding design. The RTDS simulates a power system that is developed by the user. This figure shows the RTDS draft that was built by the team to replicate the University of Idaho microgrid. The RTDS equipment provides real time analog voltages and currents to the relays to represent this system. The RTDS allows our team to change the load and power consumption as well as the utility voltage. Since the voltage and currents are sent to the relays in real time, the control algorithm in the RTAC was verified.

Runtime HMI[edit]

Runtime HMI

Runtime is the human machine interface (HMI) with the RTDS equipment. This gigure shows the Runtime model that was built so our team can interact with the RTDS hardware and manipulate the power system in real time. The main functions we implemented in Runtime are frequency and voltage control of the steam plant and utility, open and close for all breakers, and load consumption control.

Communications[edit]

High speed communication is necessary for safe, reliable, and economical power system control. Our team decided to use IEC 61850 GOOSE (Generic Object Oriented Substation Event) and MMS (Manufacturing Message Specification) communication over an Ethernet network after literature research on load shedding designs. GOOSE is used to send analog and binary signals from the relay to the RTAC. MMS is used to send trip (OC, Open Command) and close (CC, Close Command) signals from the RTAC to the relay.

Current and Voltage Amplifiers[edit]

Voltage Amplifier Test

The AE Techron LVC5050 current amplifiers and the AE Techron LV3622 voltage amplifiers were used to simulate the secondary voltage and currents from the field CT (Current Transformer) and PT (Potential Transformer). Due to hardware limitation, we supplied A-phase current and voltages only. Due to this limitation, the A-phase voltage angle is used as the reference in the relay.The RTDS output is a low-level analog. It is intended to be placed into the low side of the relay's voltage and current transformers. The relay instruction manual gives scaling factors to use for the low-level input. However, there was no recommendation for a scaling factor from the RTDS, through amplifiers, and to the relay. As such, we developed the test plan this figure to learn how the amplifiers work and to gain confidence in the output before attaching the amplifier to the relay and RTDS output.

RTDS Analog Channels

The same test was followed for the current amplifiers except a relay test kit was used in place of the function generator. The resultant scaling factors used for the 12 analog channels from RTDS are shown this Figure.

Analog Wiring

Lastly, the analog wiring for the voltage and current channels are illustrated above in figure.

Microgrid Testing Results[edit]

Testing Action Results
Transition from Grid-Tied to Microgrid The Avista utility voltage was dropped from 13.2kV to 9kV to represent a utility undervoltage event. The West Tie relay sent an undervoltage signal over GOOSE messaging to the RTAC. The RTAC sent a trip signal to the West Tie relay and islanded the university. The Jansen building breaker was tripped via internal RTDS logic since there is no physical relay controlling this breaker. The RTAC calculated how much load should be tripped and sent the corresponding trip signals to bring the total power consumption by the loads to less than 800kW.
Load Shedding Within Microgrid While in an island condition and with all priority building breakers closed, the power consumption of CNR was increased until the total load consumption was greater than 800kW. This caused an underfrequency and undervoltage event on the microgrid. The RTAC sent a trip signal to the GJL relay since this is the lowest priority building breaker currently closed. With GJL tripped, the total load consumption returned to lower than 800kW and no further load shedding is required.
Transition from Microgrid to Grid-Tied The Avista utility voltage was returned from 9kV to 13.2kV. This ends the utility undervoltage event. The West Tie stopped sending an undervoltage signal to the RTAC. The RTAC implements a synchronism check between the university microgrid and Avista grid by checking voltage magnitude, frequency, and phase angle. When the synchronism check was satisfied, the RTAC closed all building breakers and the West Tie breaker by sending close signals to all the relays.

Future Work[edit]

1. Improve on RTDS design and RTAC algorithm

2. Add relays

3. Protection design

4. Incorporation of backup generators

5. Communication network design

6. Cost/benefit analysis

7. SCADA with RTAC

Team Information[edit]

Picture Info Bio
2019 Colin Photo.jpg
Lingchao(Colin) Sun:
  • major: Electrical Engineering
  • sun2566@vandals.uidaho.edu
Colin is an overseas student from China, and loves fitness and outdoor sports. He is going to be an hardworking engineer after graduation.
Kenny Sheffler Picture.jpg
Kenny Sheffler:
  • major: Electrical Engineering
  • shef8271@vandals.uidaho.edu
Kenny is interested in working in renewable energy, power system protection, and/or microgrid design.
Simeon.jpg
Simeon Drapeau:
  • major: Electrical Engineering
  • drap4863@vandals.uidaho.edu
Simeon’s interests outside of engineering include playing baseball, basketball, and music. Inside engineering, he hopes to enter the power industry but is also opened to different fields such as microelectronics and control systems.
Mohammed.png
Mohammed Subahe:
  • major: Electrical Engineering
  • suba1208@vandals.uidaho.edu
Mohammedan is an international student at university of I daho, and he is interested in power area.

Additional Documentation[edit]

Timeline Schedule

Meeting Agendas

Meeting Minutes

Presentations

Final Report